Product description:

1. MAY is a discrete resistor network decoder, commonly known as R2R. Unlike ordinary decoders that use chips to complete, Mei uses FPGA to control and switch discrete resistor networks to convert digital signals into analog signals. In this way, the designer's algorithm can be implemented in a more flexible way, thus breaking through the limitations of the chip. The conversion of the discrete resistor network is very difficult to control, and it can be a thousand miles away. Therefore, if it is only for the sake of separation, the performance is actually not as good as the chip. For example, the SINAD (signal-to-noise ratio, the ratio of signal to distortion plus noise, also called THD+N) of the R2R chip PCM1704K can reach 9xdb, but most of the many discrete R2R decoders on the market cannot reach PCM1704K. The performance, even some have only 6xdb. Such a discrete R2R decoding usually still has the natural and smooth tone unique to the discrete R2R, but its resolution, sound field, separation, and tri-band density cannot reach the ideal, which is the so-called "blur".

2. The new generation of MAY has increased SINAD to more than 115db and DNR (dynamic range) to more than 130db. This is the highest performance of R2R audio decoders in the world today, not one of them. If you have a full understanding of audio decoder technology, you will know what this number means. Therefore, we are proud to announce that in the field of resistive network audio decoders, "Mei" represents the world's high level.

3. Each channel of MAY has an independent DAC module. Each module has 6 groups of networks on the front and the same 6 groups of networks on the back. A total of 12 groups form a fully balanced structure. Among them, 4 groups of networks constitute DSD decoding, which we call "vector step resistor network", 4 groups of networks constitute R2R structure for PCM decoding, and 4 groups of networks are used to linearly compensate R2R networks. Therefore, MAY's DSD decoding does not need to be converted to PCM, but is directly carried out by the "vector step resistor network". This technology was implemented on Spring four years ago. At that time, no one could understand such black technology, because conventional R2R cannot perform DSD decoding. This is also the pioneering work of Spring, and now some other manufacturers have also learned it. However, our "vector step resistor network" algorithm actually has some tricks that are difficult to copy. Basically, apart from the inherent noise floor of its DSD, no harmonic distortion can be observed.

4. MAY's PCM decoding is completed by 4 groups of R2R structure resistor networks. In addition, there are another 4 groups of resistor networks for linear compensation of the main R2R network. For example, an ideal value is 32768, and the actual value is 32700 due to resistance errors. The auxiliary resistor network produces a 68, which is added to the main resistor network to form an ideal value of 32768. Through this technology, we can make the equivalent resistance accuracy after compensation reach an incredible 0.00005%.

5.We must know that off-the-shelf resistors cannot achieve 0.00005% accuracy. This is why so many discrete R2R decoding can not achieve higher performance. Because accuracy determines linearity, and linearity determines harmonic distortion, IMD, and almost all AC performance. This is why the performance of so many discrete R2R decoders is only 6xdb, 7xdb, and at most 8xdb. But PCM1704K can reach 9xdb, because PCM1704K trims resistance through laser, and obtains higher precision. The spring reached 105db because of linear compensation technology. The current Mei reached 115db because of the new generation of linear compensation technology.

6. Another black technology of MAY is its powerful PLL+FIFO technology. We all know the importance of jitter. Mei uses a conventional technology, PLL (Phase Locked Loop). However, this is not an ordinary PLL, it is an extreme performance, which is similar to a perfect PLL. This PLL provides 0.1Hz, 3rd order low-pass jitter suppression capability, and uses femtosecond VCXO as the clock source of the PLL. In the test, we injected a 1.5us, 1KHz jitter into the digital input terminal. Please note that the unit is us, not ps, ns. 1.5us=1500ns=1500000ps=1500000000fs, this is an extremely exaggerated jitter, and in the actual measurement, we can see that it has been completely removed. It has no effect on the output.